The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple masking, etching, and dielectric and conductor deposition processes. Because of the high-precision required in the production of these integrated circuits, an extremely flat surface is generally needed on at least one side of the semiconductor wafer to ensure proper accuracy and performance of the microelectronic structures being created on the wafer surface. As the size of the integrated circuits continues to decrease and the density of microstructures on an integrated circuit increases, the need for precise wafer surfaces becomes more important. Therefore, between each processing step, it is usually necessary to polish or planarize the surface of the wafer to obtain the flattest surface possible.
For a discussion of chemical mechanical polishing (CMP) processes and apparatus, see, for example, Arai, et al., U.S. Pat. No. 4,805,348, issued February, 1989; Arai, et al., U.S. Pat. No. 5,099,614, issued March, 1992; Karlsrud etal., U.S. Pat. No. 5,329,732, issued July, 1994; Karlsrud, U.S. Pat. No. 5,498,196, issued March, 1996; and Karlsrud et al, U.S. Pat. No. 5,498,199, issued March, 1996.
Such polishing is well known in the art and generally includes attaching one side of the wafer to a flat surface of a wafer carrier or chuck and pressing the other side of the wafer against a flat polishing surface. During the polishing or planarization process, the workpiece or wafer is typically pressed against the polishing pad surface while the pad rotates about its vertical axis. In addition, to improve the polishing effectiveness, the wafer may also be rotated about its vertical axis and oscillated back and forth over the surface of the polishing pad.
In general, the polishing surface comprises a horizontal polishing pad that has an exposed abrasive surface of, for example, cerium oxide, aluminum oxide, fumed/precipitated silica or other particulate abrasives. Polishing pads can be formed of various materials, as is known in the art, and which are available commercially. Typically, the polishing pad may be a blown polyurethane, such as the IC and GS series of polishing pads available from Rodel Products Corporation in Scottsdale, Ariz. The hardness and density of the polishing pad depends on the material that is to be polished.
Prior art polishing machines may utilize different polishing elements, including abrasive tape polishers, rotary drum polishers, linear belt polishers, and roller style polishers. For a discussion of such semiconductor wafer polishing tools, see, for example, Morioka, et al., U.S. Pat. No. 5,509,850, issued Apr. 23, 1996 (Abrasive Tape); Morioka, et al., U.S. Pat. No. 5,569,063, issued Oct. 29, 1996; Hirose, et at., U.S. Pat. No. 5,643,056, issued Jul. 1, 1997; Kim, et al., U.S. Pat. No. 5,707,274, issued Jan. 13, 1998 (Rotary Drum); Talieh, et al., U.S. Pat. No. 5,692,947, issued Dec. 2, 1997; Meyer, et al., U.S. Pat. No. 5,722,877, issued Mar. 3, 1998; Homayoun, et al., European Pat. Application No. EP 0 696 495 A1, published Feb. 14, 1996; Shendon, PCT Application No. PCT/US96/19494, International publication date Jun. 12, 1997 (Linear Belt); Baldy, et al, U.S. Pat. No. 5,335,453, issued Aug. 9, 1994; Nakamura, U.S. Pat. No. 5,361,545, issued Nov. 8, 1994 (Roller Style).
Regardless of the method or apparatus utilized for the polishing of semiconductor wafers, the resulting flatness of the semiconductor wafer is an extremely important factor in wafer quality. Various other methods and apparatus exist which attempt to improve the resulting flatness of the semiconductor wafer during planarization. For example, U.S. Pat. No. 5,485,265, issued Jan. 23, 1996 to Salugrugan, and U.S. Pat. No. 5,562,530, issued Oct. 8, 1996 to Runnels et al., generally relate to methods to achieve a more uniform planarization of the semiconductor wafer in which a pulsing pressure is applied by the polishing surface to the wafer surface. Additionally, U.S. Pat. No. 5,510,652, issued on Apr. 23, 1996 to Burke et al., and U.S. Pat. No. 5,618,381, issued on Apr. 8, 1991 to Doan et al., generally relate to methods of depositing alternating layers of dielectric materials that possess varying degrees of hardness and then utilizing the effects produced by the different polish rates of those materials during planarization to improve the quality of the wafer surface.
Yet another alternative method known for improving the efficiency of the polishing process is disclosed in U.S. Pat. No. 5,733,177, issued Mar. 31, 1998 to Tsuchiya et al., which generally discloses a two-step process for polishing wafers. The first step requires a high down-pressure for the wafer support plate and a low rotational speed for the polishing pad as it polishes the wafer surface, followed by a quick increase in rotational speed and a quick reduction in down-pressure in an attempt to achieve a rapid reduction of the surface roughness, an improvement of the polishing efficiency, and a consequential reduction in the polishing step process time. The second step initially utilizes a medium-pressure and a low rotational speed for the polishing pad which then tapers to an even slower rotational speed in an attempt to prevent hazing of the wafer surface.
Generally, flatness is determined by the evaluation of two parameters, which include the planarity within a die structure or chip and the global uniformity of the entire semiconductor wafer. Although the aforementioned methods and apparatus seek to achieve high-precision planarization of the semiconductor wafer, generally, as one skilled in the art will appreciate, the prior art tends to optimize only one aspect of the overall flatness of the semiconductor wafer, e.g., the global uniformity of the semiconductor wafer surface or the planarity within smaller regions, generally at the expense of the other parameter. This optimization of only one aspect of the overall flatness of the semiconductor wafer surface further results in a lower process yield than what is attainable by the present invention. Thus as one skilled in the art will appreciate, a need exists for a technique which effectively optimizes the global uniformity of the entire semiconductor surface while also optimizing the planarity within an individual die structure or chip.